1. Field of the Invention
The present invention relates to a delay locked loop and, more particularly, to a delay locked loop which can generate a plurality of clock signals which have different phases from each other and a semiconductor memory device having the same.
2. Description of the Related Art
A delay locked loop is commonly employed in a control device and a semiconductor memory device to generate a plurality of clock signals which have different respective phases. Each device generates data strobe signals at a higher rate higher than externally applied clock signals using a plurality of clock signals generated from the delay locked loop and receives or outputs data in response to the data strobe signals.
FIG. 1 is a block diagram illustrating a conventional delay locked loop. The delay locked loop of FIG. 1 includes dividers 10 and 20, a phase detector 12, a first counter 14, a second counter 16, and a delay circuit 18. The delay circuit 18 includes delay cells 18-1 to 18-4 connected in a cascade configuration.
Functions of the components of FIG. 1 are explained below.
The divider 10 divides an externally applied clock signal CLK and generates a divided clock signal DCLK. The phase detector 12 detects a phase difference between a feedback clock signal FCLK and the divided clock signal DCLK at the initial stage and generates a first up signal CUP if a phase of the feedback clock signal precedes a phase of the divided clock signal DCLK and a first down signal CDN if a phase of the divided clock signal DCLK precedes a phase of the feedback clock signal. After the first down signal CDN is generated, the phase detector 12 generates a second up signal FUP if a phase of the feedback clock signal precedes a phase of the divided clock signal DCLK and a second down signal FDN if a phase of the divided clock signal DCLK precedes a phase of the feedback clock signal. That is, the phase detector 12 continuously generates the first up signal CUP at an initial stage until a phase difference between the feedback clock signal FCLK and the divided clock signal DCLK is within a predetermined range and then generates the second up signal FUP and the second down signal FDN. The first counter 14 performs an up count in response to the first up signal CUP to generate an m-bit first control signal CON1. The second counter 16 is enabled in response to the first down signal CDN, performs an up count in response to the second up signal FUP, and perform a down count in response to the second down signal FDN to perform an n-bit second control signal CON2. The delay circuit 18 receives a clock signal CLK and adjusts a delay time of the delay cells 18-1 and 18-2 in response to the m-bit first control signal CON1 and the n-bit second control signal CON2 to generate four clock signals CLK0, CLK90, CLK180, and CLK270 which have a phase difference of 90° from each other. The divider 20 divides the clock signal output from the delay 18 to generate the feedback clock signal FCLK.
However, the clock signals CLK0, CLK90, CLK180, and CLK270 generated from the conventional delay locked loop might not have an precise phase difference of 0°, 90°, 180°, and 270° due to transient phase change (noise) which results from variation of power voltage and external noise that occurs during operation.